1. Field of the Invention
The field of the invention relates to data processing and in particular to detecting transitions occurring at nodes within a circuit.
2. Description of the Prior Art
The present invention is concerned with circuits which have clocked latches or registers for receiving, storing and outputting signals, the latches being connected together by combinational logic. The signals take a finite amount of time to pass through the combinational logic, and the clocking frequency of the latches must not be so high that a signal cannot pass through the connecting combinational logic and reach a next latch within the clock cycle. If the clocking frequency is too high errors will occur.
The time taken for a signal to pass through the combinational logic is affected by a number of things such as operational voltage and temperature of the circuit. Thus, when determining an appropriate clocking frequency, different factors such as the expected operating conditions of the circuit and the tolerance of the device to occasional errors need to be considered.
Previously when determining what a suitable operational frequency of a circuit might be, synthetic circuits have been created which replicate the circuit under question. These synthetic circuits are designed so that the timing can be easily observed, and they try to imitate the delay dependencies of the circuit they are mimicking. Example signals are run and the real circuit is calibrated against them. An alternative has been to identify the critical paths of the real circuit and to build delay/parametric circuits that attempt to match these paths. Precise matching of circuits and paths is becoming harder and harder as these get smaller due to localised variation and parasitic noise effects caused by neighbouring elements. There are also delays due to parasitic noise in system elements such as clock trees or power girds and these are not deterministic.
It would be desirable to be able to accurately determine a suitable operating frequency of a circuit.